What Is A Testbench

Part of the Fundamentals section of Coddy's Verilog journey — lesson 73 of 90.

A testbench is a special Verilog module used to test another module. It provides inputs to your design and checks if the outputs are correct.

Why Do We Need a Testbench?

When you build a module, you need to make sure it works correctly. A testbench allows you to:

Apply different input values to your module
Observe the outputs

Check if the outputs match what you expect
Do this automatically without manual testing

Testbench vs Design Module

	Design Module	Testbench
Purpose	Implements hardware	Tests the design module
Has ports?	Yes (inputs and outputs)	No (self-contained)
Synthesizable?	Yes	No (simulation only)

Simple Testbench Example

module testbench;              // No ports!

  // The inputs and outputs come from the module we are testing (the DUT).
  reg a, b;                    // reg for inputs
  wire c;                      // wire for output
  

  // This is module instantiation — it creates a copy of the and_gate module and names it dut
  and_gate dut (               // Instantiate DUT
    .a(a),
    .b(b),
    .c(c)
  );

  // This is an initial block that applies test values to the inputs of the module being tested.
  initial begin                // Apply test values
    a = 0; b = 0; #10;
    a = 0; b = 1; #10;
    a = 1; b = 0; #10;
    a = 1; b = 1; #10;
    $finish;
  end
endmodule

Key Points

Testbench has no ports
reg is used for signals that change (inputs to DUT)
wire is used for signals from DUT (outputs)

The module being tested is called DUT (Design Under Test)
$finish ends the simulation

We will cover creating stimulus, displaying results, and other testbench features in the following lessons.

Challenge

You are given an AND gate module. Your task is to add the missing parts to its testbench.

What to do:

Add the following parts to the testbench:

Declare reg for inputs a and b
Declare wire for output c
Instantiate and_gate with name dut and connect the ports

Cheat sheet

A testbench is a Verilog module used to test another module (the DUT - Design Under Test). It has no ports and is simulation-only.

module testbench;              // No ports!

  reg a, b;                    // reg for inputs (signals that change)
  wire c;                      // wire for DUT outputs

  and_gate dut (               // Instantiate DUT
    .a(a),
    .b(b),
    .c(c)
  );

  initial begin                // Apply test values
    a = 0; b = 0; #10;
    a = 1; b = 1; #10;
    $finish;                   // End simulation
  end
endmodule

Use reg for signals driven in initial blocks (inputs to DUT)
Use wire for signals coming from the DUT (outputs)
$finish ends the simulation

Try it yourself

module and_gate (
  input a,
  input b,
  output c
);
  assign c = a & b;
endmodule

module testbench;
  
  // Task 1: Declare reg for inputs a and b
  
  
  // Task 2: Declare wire for output c
  

  // Task 3: Instantiate and_gate with name dut
  // Connect .a(a), .b(b), .c(c)


  initial begin
    a = 0; b = 0; #10 $display("%d & %d = %d", a, b, c);
    a = 0; b = 1; #10 $display("%d & %d = %d", a, b, c);
    a = 1; b = 0; #10 $display("%d & %d = %d", a, b, c);
    a = 1; b = 1; #10 $display("%d & %d = %d", a, b, c);
    $finish;
  end
endmodule