Assignment Delays

Part of the Fundamentals section of Coddy's Verilog journey — lesson 69 of 90.

In previous lessons, we covered general delays (#10 a = b;) and gate delays (and #5 (out, a, b);). Now we cover assignment delays, which are delays that occur inside a procedural block (like initial or always) as part of an assignment statement.

An assignment delay waits for a specified time, then performs the assignment. The delay is placed after the # symbol and before the assignment.

Syntax:

variable = #delay expression;

Unlike a general delay #10 a = b; (delay then assign), an assignment delay a = #10 b; takes the value of b at that moment, waits 10 time units, then assigns it to a.

Assignment Delay vs General Delay

	General Delay	Assignment Delay
Syntax	`#10 a = b;`	`a = #10 b;`
When is value read?	At time of assignment (after delay)	Immediately (before delay)
What value is assigned?	Value of `b` at that moment	Value of `b` at time 0 (or read time)
When is value assigned?	After delay	After delay

Example: The Difference

initial begin
  b = 1;
  #5 b = 0;
  
  // General delay
  #10 a1 = b;     // Waits 10, then reads b (b=0) → a1=0
  
  // Assignment delay
  a2 = #10 b;     // Reads b now (b=0), waits 10, then assigns → a2=0
end

Both give the same result here. The difference appears when b changes during the delay.

Key Difference Example

To show b changing during the delay, we need two separate initial blocks that run in parallel:

initial begin
  b = 1;
  a1 = #10 b;     // Reads b=1 at time 0, assigns a1=1 at time 10
end

initial begin
  #5 b = 0;       // Changes b to 0 at time 5 (during the delay)
end

At time 0: a1 reads b = 1
At time 5: b changes to 0 (while a1 is still waiting)
At time 10: a1 is assigned 1 (the value read at time 0), not 0

With a general delay #10 a2 = b; in a separate block, b would be read at time 10 (value 0).

Important Rules

Rule	Explanation
`=` goes before `#`	`a = #10 b;` not `a #10 = b;`
Value is read immediately	Right side evaluated right away
Assignment happens after delay	Left side gets value later
Only for procedural blocks	Used in `initial` or `always`

Challenge

What to do:

Add the missing assignment delay so that a gets the value of b after 15 time units, but reads b immediately.

Cheat sheet

Assignment delay reads the right-hand side immediately, waits the delay, then assigns:

variable = #delay expression;

Key difference vs general delay:

	General Delay `#10 a = b;`	Assignment Delay `a = #10 b;`
Value of b read	After delay	Immediately
Value assigned	After delay	After delay

When b changes during the delay, results differ:

initial begin
  b = 1;
  a1 = #10 b;   // Reads b=1 now, assigns a1=1 at time 10
  #5 b = 0;     // b changes at time 5 — a1 still gets 1
  // With #10 a2 = b; → reads b=0 at time 10, so a2=0
end

Only valid inside procedural blocks (initial or always).

Try it yourself

module assignment_challenge;
  reg a, b;
  
  // Separate block to change b during the delay
  initial begin
    b = 1;
    // TODO: Add assignment delay
    // a should get b after 15 time units
    // Read b now, assign after delay

  end
  
  initial begin
    #5 b = 0;      // Changes b during the delay
    #20 $display("Time %0t: a = %b", $time, a);
    $finish;
  end
endmodule