Input And Output Ports

Part of the Fundamentals section of Coddy's Verilog journey — lesson 31 of 90.

Input and output ports are the connections that allow a module to communicate with the outside world. They are like the pins on a chip. Ports are the interface between a module and the rest of the design.

Every module has:

Input ports — signals that come into the module
Output ports — signals that go out of the module

Input Ports

Input ports receive data from outside. They cannot be changed inside the module—only read.

input clk;        // Single-bit input
input [7:0] data; // 8-bit input vector
input a, b;       // Multiple inputs on one line

Rules for inputs:

Cannot be assigned a value inside the module
Cannot be declared as reg
Always wire (by default)

Output Ports

Output ports send data to the outside. They can be driven by assign or always blocks.

output out;           // Single-bit output
output [3:0] result;  // 4-bit output
output reg busy;      // Output can be reg
output wire ready;    // Output can be wire

Rules for outputs:

Can be wire (with assign) or reg (with always)
Must be driven by something inside the module

Port Declaration Syntax

Port declaration syntax is the specific way you write input and output ports in a module. It tells Verilog three things about each port:

Direction — is it input, output, or inout?
Size — how many bits wide is it?
Name — what is it called?

module example (
  input [7:0] data_in,    // Input vector
  input clk,              // Single input
  input enable,           // Single input
  output reg [7:0] out,   // Output reg
  output busy             // Output wire
);

Why Port Direction Matters

The direction tells Verilog:

Which signals the module can read (inputs)
Which signals the module can write (outputs)
What types of connections are allowed

Using wrong direction causes compilation errors.

Code Example

module port_demo (
  input [3:0] a,        // Can only read
  input [3:0] b,        // Can only read
  output reg [3:0] sum, // Can write (reg)
  output [3:0] diff     // Can write (wire)
);
  always @(*) begin
    sum = a + b;        // Writing to output reg
  end
  
  assign diff = a - b;   // Writing to output wire
endmodule

Challenge

Complete the Port Declarations

What to do:

Add an 8-bit input called data_in
Add a single-bit input called clk
Add a 4-bit output called result (use reg — will be assigned in always block)
Add a single-bit output called valid (use wire — will be assigned with assign)

Cheat sheet

Ports are the interface between a module and the outside world.

Input Ports

Inputs are always wire, read-only inside the module:

input clk;        // Single-bit
input [7:0] data; // 8-bit vector
input a, b;       // Multiple inputs

Output Ports

Outputs can be wire (driven by assign) or reg (driven by always):

output wire ready;    // Use with assign
output reg busy;      // Use with always

Port Declaration in Module Header

Each port declaration specifies direction, size, and name:

module example (
  input [7:0] data_in,   // 8-bit input
  input clk,             // single-bit input
  output reg [3:0] sum,  // 4-bit output reg
  output diff            // single-bit output wire
);
  always @(*) sum = data_in[3:0] + 1;
  assign diff = data_in[0];
endmodule

Try it yourself

module port_challenge (
  // Task 1: Add an 8-bit input called data_in
  
  
  // Task 2: Add a single-bit input called clk
  
  
  // Task 3: Add a 4-bit output called result (use reg)
  
  
  // Task 4: Add a single-bit output called valid (use wire)
  
  
);

  reg [3:0] counter;
  
  always @(posedge clk) begin
    counter <= counter + 1;
    result <= counter;
  end
  
  assign valid = (counter > 8);
  
endmodule